In recent years, memory latency has become a major concern in computing. For example, memory latency affects the response time of electronic components, such as displays and videos. Memory latency also impacts the die area expended on latency buffers.
Many electronic systems require certain timing requirements to be maintained with respect to memory subsystems. For example, a dynamic random access memory (DRAM) requires certain timing such as read/write cycle time, access time, pre-charge time, page mode read/write cycle, etc. By issuing memory requests in particular orders, these timing requirements can be maintained while increasing the efficiency of the memory subsystem. By increasing the efficiency, bandwidth increases. However, if the arbiter focuses too heavily on increasing bandwidth, latency may increase as some requests are being bypassed too long as more efficient requests are being processed.
Also, if the arbiter focuses too heavily on latency, then memory requests may be sent to the memory subsystem in sequences that do not provide for efficient use of the memory subsystem, thereby decreasing bandwidth.
Accordingly, better arbiters are needed to address the trade-off between memory latency and memory bandwidth.